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1 ? fn6059.1 hi-200/883 dual spst cmos analog switch the hi-200/883 is a monolithic device comprising two independently selectable spst s witchers which feature fast switching speeds (240ns typical) combined with low power dissipation (15mw typical @ +25c) each switch provides low ?on? resistance operation for input signal voltages up to the supply rails and for signal currents up to 25ma continuous. rugged di construction eliminates latch-up and substrat e scr failure modes. all devices provide break-before-make switching and are ttl and cmos compatible for maximum application versatility. hi-200/883 is an ideal component for use in high frequency analog switching. typical applications include signal path switching, sample and hold circuits, digital filters, and op amp gain switching networks. hi-200/883 is available in a 14 pin ceramic dip package and a 10 pin metal can (to-100) package. functional diagram features ? this circuit is processed in accordance to mil-std-883 and is fully conformant under the provisions of paragraph 1.2.1. ? low ?on? release . . . . . . . . . . . . . . . . . . . . . . .100 ? max ? wide analog signal range . . . . . . . . . . . . . . . . . . . .15v ? ttl/cmos compatible . . . . . . . . . . . . . . 2.4v (logic ?1?) ? turn-on time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns ? analog current range (continuous) . . . . . . . . . . . . 25ma ? no latch-up ? replaces dg200 applications ? high frequency analog switching ? sample and hold circuits ? digital filters ? op amp gain switching networks reference, level shifter, and driver gate switch cell source drain output logic input v+ v ref v- input gate pinouts hi1-200/883 (cerdip) top view hi2-200/883 (metal can) top view a 2 nc gnd nc in2 out2 v- a 1 nc v+ nc in1 out1 v ref 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v+ out1 out2 in2 a 2 2 5 3 10 4 8 9 7 6 in1 v ref v- gnd a 1 1 data sheet september 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners. o b s o l e t e p r o d uc t n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e rs i l o r w w w . i n t e r s i l . c o m / t s c
2 absolute maximum rati ngs thermal information voltage between v+ and v- terminals . . . . . . . . . . . . . . . . . . . .40v v supply to ground (v+, v-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v analog input voltage, (+v s ) . . . . . . . . . . . . . . . . . . +v supply +2v analog input voltage, (-v s ) . . . . . . . . . . . . . . . . . . . . -v supply -2v digital input voltage, (+v a ) . . . . . . . . . . . . . . . . . . . +v supply +4v digital input voltage, (-v a ). . . . . . . . . . . . . . . . . . . . . -v supply -4v peak current (s or d) (pulse at 1ms, 10% duty cycle max). . . . . . . . . . . . . . . . . . 40ma continuous current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature (soldering 10 sec) . . . . . . . . . . . . . . . . . . . 275c thermal resistance ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 80 24 metal can package . . . . . . . . . . . . . . . 160 75 package power dissipation at +75 o c ceramic dip package . . . . . . . . . . . . . . . . . . . . . . . . . . 0.76w/ o c metal can package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.62w/ o c package power dissipation derating factor above +75 o c ceramic dip package . . . . . . . . . . . . . . . . . . . . . . . 10.08mw/ o c metal can package . . . . . . . . . . . . . . . . . . . . . . . . . . 8.24mw/ o c recommended operating conditions operating temperature range . . . . . . . . . . . . . . . -55 o c to +125 o c operating supply voltage range (v supply ) . . . . . . . . . . . . . . 15v analog input voltage (v s ) . . . . . . . . . . . . . . . . . . . . . . . . v supply logic low level (v al ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 0.8v logic high level (v ah ) . . . . . . . . . . . . . . . . . . . . 2.4v to + v supply caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. table 1. d.c. electrical performance specifications device tested at: + v supply = + 15v, ? v supply = ? 15v, v ref = open, gnd = 0v, unless otherwise specified. d.c. parameters symbol conditions group a subgroups temperature ( o c) min max units switch ?on? resistance r ds v a = 0.8v, v s = 10v, i d = -1ma, all unused channels v a = 0.8v 125-70 ? 2, 3 -55 to 125 - 100 ? v a = 0.8v, v s = -10v, i d = 1ma, all unused channels v a = 0.8v 125-70 ? 2, 3 -55 to 125 - 100 ? source ?off? leakage current i s(off) v s = +14v, v d = -14v, v a = 2.4v, all unused channels v a = 2.4v, v d = +14v, v s = -14v 125-55na 2, 3 -55 to 125 -500 500 na v s = -14v, v d = +14v, v a = 2.4v, all unused channels v a = 2.4v, v d = -14v, v s = +14v 125-55na 2, 3 -55 to 125 -500 500 na drain ?off? leakage current i d(off) v d = -14v, v s = +14v, v a = 2.4v, all unused channels v a = 2.4v, v d = +14v, v s = -14v 125-55na 2, 3 -55 to 125 -500 500 na v d = +14v, v s = -14v, v a = 2.4v, all unused channels v a = 2.4v, v d = -14v, v s = +14v 125-55na 2, 3 -55 to 125 -500 500 na channel ?on? leakage current i d(on) v d = v s = +14v, v a = 0.8v, all unused channels v a = 0.8v, v d = v s = -14v 125-55na 2, 3 -55 to 125 -500 500 na v d = v s = -14v, v a = 0.8v, all unused channels v a = 0.8v, v d = v s = +14v 125-55na 2, 3 -55 to 125 -500 500 na low level input current i al v al = 0.8v all channels v a = 2.4v 125-1.01.0 a 2, 3 -55 to 125 -1.0 1.0 a high level input current i ah v ah = 2.4v all channels v ah = 4.0v 125-1.01.0 a 2, 3 -55 to 125 -1.0 1.0 a supply current +i cc all channels v a = 0v 1 25 - 2.0 a 2, 3 -55 to 125 - 2.0 a all channels v a = 3v 1 25 - 2.0 ma 2, 3 -55 to 125 - 2.0 ma hi-200/883
3 supply current -i cc all channels v a = 0v 1 25 -2.0 - a 2, 3 -55 to 125 -2.0 - a all channels v a = 3v 1 25 -2.0 - a 2, 3 -55 to 125 -2.0 - a table 1. d.c. electrical performance specifications (continued) device tested at: + v supply = + 15v, ? v supply = ? 15v, v ref = open, gnd = 0v, unless otherwise specified. d.c. parameters symbol conditions group a subgroups temperature ( o c) min max units table 2. a.c. electrical performance specifications device tested at: + v supply = + 15v, ? v supply = ? 15v, v ref = open, gnd = 0v, unless otherwise specified. parameters symbol conditions group a sub- groups temperature ( o c) min max units turn ?on? time t on c l = 35pf, r l = 1k ? 9 25 - 500 ns 10, 11 55 to 125 - 800 ns turn ?off? time t off c l = 33pf, r l = 1k ? 9 25 - 500 ns 10, 11 55 to 125 - 650 ns table 3. electrical performan ce specifications (note 1) device tested at: + v supply = + 15v, ? v supply = ? 15v, v ref = open, gnd = 0v parameters symbol conditions note temperature ( o c) min max units address capacitance c a f = 1mhz, v al = 0v 1 25 - 20 pf switches input capacitance c s (off) f = 1mhz, v ah = 5v, measured source to gnd 1 25 - 20 pf switch output capacitance c d (off) f = 1mhz, v ah = 5v, measured output to ground 1 25 - 20 pf c d (on) f = 1mhz, v al = 0v, measured output to ground 1 25 - 30 pf drain to source capacitance c ds f = 1mhz, v ah = 5v 1 25 - 2.0 pf off isolation v iso f = 200khz, v a = 2.4, r l = 1k, v gen = 1v p-p, c l = 10pf 12555-db cross talk v ct f = 200khz, v a = 2.\4, r l = 1k, v gen = 1v p-p, c l = 10pf 12560-db charge transfer error v cte f = 200khz, v a = 0 to 4v, c l = 0.01f 1 25 -10 10 mv note: 1. parameters listed in table 2 are controlled via design or process parameters and are not dire ctly tested at final production. these parameters are lab characterized upon initial design re lease, or upon design changes. these param eters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. table 4. electrical test requirements mil-std-883 test requirements subgroups (tables 1 and 2) interim electrical parameters (pre burn-in) 1 final electrical test parameters 1 (note 2), 2, 3, 9, 10, 11 group a test requirements 1, 2, 3, 9, 10, 11 groups c & d endpoints 1 note: 2. pda applies to subgroup 1 only. hi-200/883
4 test circuits figure 1. input leakage current figure 2. i d (off) figure 3. i s (off) figure 4. i d (on) figure 5. supply currents figure 6. charge transfer error +v cc d -v cc gnd s i in v in +v cc d -v cc gnd v s i d v in v d s +v cc v d -v cc gnd i s v s s v in +v cc d -v cc gnd v in i d(on) v s gnd i 1 +v cc d s v in i 2 -v cc hi-200/883
5 figure 7. r ds figure 8. off channel isolation figure 9. crosstalk between channels test circuits (continued) +v cc -v cc gnd v in v d d s hi-200/883
6 switching waveforms figure 10. figure 11. figure 12. hi-200/883
7 burn-in circuits figure 13. hi-200/883 ceramic dip figure 14. hi-200/883 metal can (to-99) notes: 3. r 1 = r 2 = 10k ? 4. c 1 = c 2 = 0.01f (per socket) or 0.1f (per row) 5. d 1 = d 2 = in4002 or equivalent 6. |(v+) - (v-)| = 30v hi-200/883
8 schematic diagrams ttl/cmos reference circuit v ref cell switch cell v+ gnd r 2 5k m p13 q p1 q n1 r 3 24.2k r 4 5.4k r 5 7.9k r 6 300 q p2 q p3 q p5 q p4 q n4 q n2 m n14 m n15 m n16 m n17 v- gnd r 7 100k v ll to p 2 v ref d 3 a? input a ? v+ p11 n12 n13 v- p12 n11 output hi-200/883
9 digital input buffer and level shifter schematic diagrams (continued) p3 p1 n1 to v ll to v ref p2 n2 200 ? d 1 d 2 v- va p4 p5 n6 p7 p6 n7 n5 n4 n3 v- v+ p8 p9 p10 n8 n9 n10 input p11 n12 n13 p12 n11 output v+ v- r 1 test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v and v ref = open figure 15. on resistance vs temperature figure 16. on resistance vs analog signal level and power supply voltage 80 70 60 50 40 30 20 10 0 -25 -50 0 25 50 75 100 125 on resistance ( ? ) temperature ( o c) v in = 0v 100 50 0 -15 -10 -5 0 5 10 15 analog signal level (v) on resistance ( ? ) v+ = +12.5v v- = -12.5v v+ = +10v v- = -10v v+ = +15v v- = -15v hi-200/883
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com figure 17. leakage current vs temperat ure figure 18. switch current vs voltage figure 19. off isolation vs frequency test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v and v ref = open (continued) 100 10 1.0 0.1 current (na) 25 50 75 100 125 temperature ( o c) i d(on) i s(off) / i d(off) 90 80 70 60 50 40 30 20 10 0 01234567 voltage across switch ( v) switch current (ma) 140 120 100 80 60 40 20 0 100hz 1khz 10khz 100khz 1mhz frequency (hz) off isolation (db) r l = 1k ? hi-200/883
11 die characteristics die dimensions: 54 mils x 79mils x 19 mils metallization: type: aluminum thickness: 16k ? 2k ? glassivation: type: nitride over silox silox thickness: 12k ? 2k ? nitride thickness: 3.5k ? 1k ? die attach: material: gold/silicon eutectic alloy temperature: ceramic dip - 460c (max) temperature: metal can - 420c (max) worst case current density: 2 x 10 5 a/cm 2 at 25ma metallization mask layout hi-200 v- v ref in 1 out 1 4 5 6 7 8 3 gnd a 2 a 1 v+ 9 10 1 2 in 2 out 2 hi-200/883

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